My Slides On Nehalem & Core i7 – i5 – i3 Processors
July 4, 2010 4 Comments
Recently I had a presentation on Science & Mine University and you can download it Here (Nehalem & Core i7 – i5 – i3 Architecture).
This presentation was presented by Gaurang Kher & Saahithi Gunda at Electrical and Computer Engineering at University of Illinois at Chicago. You can find the main presentation here. But note that my presentation is a newer edition of this one. I removed and add some new parts to it. Especially in Nehalem section. Actually my presentation was about Nehalem And Core i7 processors so that I decide to find a robust one and add my contents to it. I gather information from Wikipedia, Intel and another website and you can find all of them in those websites.
This is the short description of my presentation.
- Integrated Memory Controller
- Quick Path Interconnect (QPI) & DMI
- Advanced Configuration and Power States
- Improvements to the pipeline (L2 Branch Predictor, Renamed Returned Stack Buffer, L2 TLB, etc)
- SSE 4.2 instructions
- Nehalem architecture has a three-level cache
Core-i series processors using these architectures
- Gulftown (which used Westmere architecture instead of Nehalem which is a shrinked version of Nehalem)
You can find the complete information of these architectures and other part of it in My Presentation.
On the other hand, Recently Masoud Ramezani, one of my collegues enabled RTL functionality for ScrewTurn Wiki, which let Middle East users using this useful wiki, easier than before. He also provide a Persian Translation of ScrewTurn Wiki and it is currently available on the official website. If you do not know that what is a wiki, you can read this article.